Memory cell array is an important component in modern digital systems, and is often a bottleneck of power consumption in the system design. As the demand for portable devices increases in the market, it requires higher technique for reducing power consumption in memory cell arrays. Sub-threshold design is a focus in extremely low power design nowadays. By reducing the supply voltage (Vdd) gets into the sub-threshold area of circuit—Vdd is lower than the threshold voltage (Vth), so that the system can operate in the linear range of the circuit, and thereby the dynamic and static power consumption of the system can be reduced significantly. The design of sub-threshold memory cell array further highlights the advantage of sub-threshold design in low power consumption. However, in the actual implementation process, the said design introduces a series of problems: 1) the static noise margin (SNM) is degraded severely; 2) the writing performance is weakened; 3) the tolerance to process deviations is degraded, etc. To solve these problems, some sub-threshold memory cells that can be operate at 200˜300 mV have been put forward. However, all these designs are implemented at the expense of the density of memory cells.
In a normal state, the read noise margin is the smallest when compared with the hold noise margin and the write noise margin. Therefore, the read noise margin is a key in memory cell design. In some designs, two NMOS transistors are added on the basis of six-transistor memory cell design, so that the data in internal nodes will not be affected in the process of reading out the internal data in the memory cell. In such designs, the read noise margin of the sub-threshold memory cell is equal to the hold noise margin of the memory cell. However, when compared with the conventional six-transistor memory cells, the memory cells in such a structure consume 30% more area. A single-end six-transistor sub-threshold memory cell is put forth. Though the robustness of a memory cell in such a single-end structure is higher in the reading process, the writing performance of the structure is lower, and the aid of a write-assist unit is required in the writing process. In addition, in order to solve the problem of susceptibility of the sub-threshold circuit to process deviations, the said design commonly employs transistors in a larger size. As a result, the density obtained in the design is also effected to a certain extent.
With sub-threshold design technique, the power consumption of the system can be reduced by square. The sub-threshold memory circuit design is proven that the dynamic and static power consumption of the memory cells can be reduced by square along with the supply voltage decreasing. In view of the capacity of the memory cell array, the reduction of the power consumption is highly considerable. However, a circuit operating in its sub-threshold area has unique circuit characteristics. The approach of making trade-off among reading performance, writing performance and chip area of a memory cell by adjusting the size of transistors in the memory cell in the conventional design (in the super-threshold state) is completely unable to meet the demand of sub-threshold circuit design. Therefore, the design of high-density and high-robustness sub-threshold memory cell is the bottleneck in the sub-threshold circuit design walking up to industrialization.